Professeur des universités à l’UJF (IMAG/VERIMAG) et responsable du projet MARAE au niveau de l’UJF, Saddek Bensalem a également reçu lors de cet événement un des trois prix de la meilleure publication scientifique des programmes de recherche qui ont été remis par les dirigeants des groupes EADS, Safran et Thalès.
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Best scientific publication prize for Saddek Bensalem
Financement du projet MARAE, prix de la meilleure publication scientifique des programmes de recherche. Le laboratoire VERIMAG est doublement distingué par la Fondation de Recherche pour l’Aéronautique et l’Espace
View online : http://www.ujf-grenoble.fr/12749657...
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- Seminars
- 16 May 2024 Gaiyun Liu: Modeling, analysis, and supervisory control of networked discrete event systems
- 30 May 2024 Mohamed Maghenem: A hybrid-systems framework for distributed gradient-based estimation
- 27 June 2024 Nicolas Chappe: Tba (toward a verified compilation infrastructure for concurrent programs)
Seminars
New publications
- Some Recent Publications
- Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond: Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
- Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard: Formally Verifying Optimizations with Block Simulations
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing Synchronous Unison in Directed Networks
- Karine Altisen, Pierre Corbineau, Stéphane Devismes: Certification of an exact worst-case self-stabilization time
Jobs and internships
- Jobs and internships
- [Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
- PERSYVAL Master 2 Scholarships
- [Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
- [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
- [Funded PhD] Quantitative analysis of software security against adaptive attacks
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
- [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences